The present invention relates generally to digital graphic display processors and in particular, to a hardware based dual channel block texturing and complex clipping processor for use in a graphics cogenerator.
Real time digital electronic displays are used in such applications as military command and control workstations and air-traffic control systems. In such displays, the displayed information typically comprises real-time processed data generated by a host processor which in turn receives real-time information from such devices as radars, communications equipment, and other data processors. This real-time data is combined with one or more graphic primitives, alpha-numerics, mask areas, and texture patterns to provide a comprehensive graphic display. In contemporary systems the various components of the graphics display such as primitives, mask windows, texturing and the like are provided by either a general purpose computer based graphics generator or by a hardware specific graphics generator. Of these, the general purpose graphics generators are versatile but sacrifice system performance for programmability. Hardware specific graphics generators, called cogenerators, provide good performance at the cost of programming capability. Hardware specific cogenerators are less flexible and usually require a specific system architecture for proper implementation.
Increasing demands on military command and control systems, military and civil air-traffic control system, and the like, create a need for a high performance graphics cogenerator which also provides a versatile and easily implemented programming capability. A key element in such a cogenerator is a processor that generates multiple texture patterns and defines mask windows. Such a processor is referred to as a block texturing and clip mask processor. In contemporary graphics cogenerators, block texturing and clip mask processors are typically single channel devices which require repetitive retrieval of texture patterns from a remote memory and are capable only of performing simple mask functions. It is therefore desirable to provide a block texturing and clip mask processor that is capable of performing complex mask functions, that is, masking functions, wherein mask windows are variously configured and wherein one mask window overlays another.
It is therefore and objective of the present invention to provide an improved graphics cogenerator that includes a dual block texturing and complex masking processor. It is another objective of the invention to provide a hardware based cogenerator having a very high performance block texturing and complex clip mask processor. Yet another objective of the invention is to provide a graphics cogenerator that incorporates a dual channel, hardware based block texturing and complex clipping processor. Still another objective of the invention is to provide a dual channel and complex clipping processor that provides a versatile and easily implemented programming capability.